The present invention generally relates to microelectronic device packages and, more specifically, to establishing pin connections to ceramic substrate pads used in such packaging. Glass ceramic substrates commonly used in the packaging of microelectronic semiconductor circuit chips have comparatively low strength and fracture toughness. Multilayered thin film structures (pads) are formed upon such glass ceramic substrates to provide electrical interconnections between circuit points, contained within the substrate, and input-output pins from the next level of packaging as well as circuit points from semiconductor circuit chips mounted upon the substrates. The pins are brazed to the pads. This typical structural arrangement is shown in U.S. Pat. No. 4,835,593, issued on May 30, 1989, to Anthony F. Arnold, et al., and assigned to the present assignee.
Due to the inherent fragile nature of the glass ceramic material of the substrate, there is the problem of glass ceramic cracking, particularly caused by stresses induced by the brazing of the aforementioned pins to the substrate pads. One known technique for reducing such cracking is taught in U.S. Pat. No. 4,672,739, issued Jun. 16, 1987 to Robert W. Churchwell, et al., and assigned to the present assignee. In accordance with the '739 patent, stress originates partly from the brazed joint between pad and pin which stress is directed to the underlying ceramic substrate. The stress is greatest around the edges of the pad. When the stress reaches a sufficient level, the ceramic beneath the pad fractures, causing the pin and the pad to be mechanically separated from the substrate. In order to reduce stress around the pad edges, the '739 patent provides a dielectric layer dam which covers the perimeter of each pad to prevent the brazing liquid from coming into contact with that perimeter by confining the brazing liquid to the central region of the pad surrounding the pin. The '739 patent also notes a prior art stress reduction technique whereby each entire pad surface area is divided into a number of smaller wettable surface areas, each smaller area having a surrounding non-wettable region, the brazing alloy adhering only to each surrounded wettable area. However, the total effective cross-sectional area occupied by all the smaller brazed points is significantly less than that of the entire pad. Thus, the strength and the electrical resistance of the bond between total pad and substrate are adversely affected. The latter technique also is described in connection with a solder bond in R. W. Noth, "Solder Bond", IBM Technical Disclosure Bulletin, Vol. 17, No. 8, Jan. 1975, page 2214.